Finfet device with a graphene gate electrode and methods of forming same

ABSTRACT

One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the manufacture ofsophisticated semiconductor devices, and, more specifically, to a FinFETdevice with a gate electrode comprised of graphene and various methodsof forming such FinFET devices.

2. Description of the Related Art

The fabrication of advanced integrated circuits, such as CPU's, storagedevices, ASIC's (application specific integrated circuits) and the like,requires the formation of a large number of circuit elements in a givenchip area according to a specified circuit layout, wherein so-calledmetal oxide field effect transistors (MOSFETs or FETs) represent oneimportant type of circuit element that substantially determinesperformance of the integrated circuits. A FET is a planar device thattypically includes a source region, a drain region, a channel regionthat is positioned between the source region and the drain region, and agate electrode positioned above the channel region.

To improve the operating speed of FETs, and to increase the density ofFETs on an integrated circuit device, device designers have greatlyreduced the physical size of FETs over the years. More specifically, thechannel length of FETs has been significantly decreased, which hasresulted in improving the switching speed of FETs. However, decreasingthe channel length of a FET also decreases the distance between thesource region and the drain region. In some cases, this decrease in theseparation between the source and the drain makes it difficult toefficiently inhibit the electrical potential of the source region andthe channel from being adversely affected by the electrical potential ofthe drain. This is sometimes referred to as a so-called short channeleffect, wherein the characteristic of the FET as an active switch isdegraded. Due to rapid advances in technology of the past several years,the channel length of FET devices has become very small, e.g., 20 nm orless, and further reductions of the channel length are desired andperhaps anticipated, e.g., channel lengths of approximately 10 nm orless are anticipated in future device generations.

In contrast to a FET, which has a planar structure, there are so-called3D devices, such as an illustrative FinFET device, which is a3-dimensional structure. More specifically, in a FinFET, a generallyvertically positioned fin-shaped active area is formed and a gateelectrode encloses both sides and an upper surface of the fin-shapedactive area to form a tri-gate structure so as to use a channel having a3-dimensional structure instead of a planar structure. In some cases, aninsulating cap layer, e.g., silicon nitride, is positioned at the top ofthe fin and the FinFET device only has a dual-gate structure. Unlike aplanar FET, in a FinFET device, a channel is formed perpendicular to asurface of the semiconducting substrate so as to reduce the physicalsize of the semiconductor device. Also, in a FinFET, the junctioncapacitance at the drain region of the device is greatly reduced, whichtends to reduce at least some short channel effects.

With respect to either a FET or a FinFET, threshold voltage is animportant characteristic of a transistor. Simplistically, a transistorcan be viewed as a simple ON-OFF switch. The threshold voltage of atransistor is the voltage level above which the transistor is turned“ON” and becomes conductive. That is, if the voltage applied to the gateelectrode of the transistor is less than the threshold voltage of thetransistor, then there is no current flow through the channel region ofthe device (ignoring undesirable leakage currents, which are relativelysmall). However, when the voltage applied to the gate electrode exceedsthe threshold voltage, the channel region becomes conductive, andelectrical current is permitted to flow between the source region andthe drain region through the conductive channel region.

There are many situations where it would be desirable to have theability to produce transistor devices with different threshold voltages.For example, low threshold voltage levels are desirable in devices inthe critical path of a circuit because such devices must operate at veryhigh speeds and they need to be able to drive a lot of current. Asanother example, it is desirable that the devices used to make an SRAMdevice have a relatively high threshold voltage so that the standbypower consumption for the SRAM device is relatively low. The capabilityof producing integrated circuit products with transistors that havediffering threshold voltages will provide circuit designers withincreased flexibility in designing increasingly complex integratedcircuit products.

Various techniques have been employed in attempts to vary or control thethreshold voltages of transistor devices. One technique involvesintroducing different dopant levels into the channel regions ofdifferent transistors in an effort to produce devices having differentthreshold voltages. However, given the very small channel length oncurrent and future device generations, e.g., 10 nm gate length, it isvery difficult to uniformly dope such a small area of the substrate dueto inherent variations in the ion implanting process that are typicallyperformed to introduce such dopant materials. As a result of lack ofuniformity in the channel doping, this technique has resulted in deviceshaving reduced performance capability and/or undesirable or unacceptablevariations in the threshold voltage of such devices as compared todesired or target threshold voltages of such devices.

Another technique for manufacturing devices having different thresholdvoltage levels involves including so-called work-function adjustingmetals, such as lanthanum, aluminum and the like, as part of the gatestructures of various devices, i.e., N-channel transistors and P-channeltransistors, respectively. However, as the gate length of thetransistors has decreased, it has become increasingly more challengingto effectively and efficiently incorporate such additional materialsinto the gate structure. Even if there is sufficient room for suchadditional work-function adjusting materials, the fabrication of suchdevices is extremely complex and time consuming

The present disclosure is directed to various methods of forming FinFETdevices that may solve or at least reduce one or more of the problemsidentified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure is directed to a FinFET device with agate electrode comprised of graphene and various methods of forming suchFinFET devices. One illustrative device disclosed herein includes atleast one fin comprised of a semiconducting material, a layer of gateinsulation material positioned adjacent an outer surface of the fin, agate electrode comprised of graphene positioned on the layer of gateinsulation material around at least a portion of the fin and, aninsulating material formed on the gate electrode.

One illustrative method disclosed herein involves forming at least onefin in a semiconducting substrate, forming a layer of gate insulationmaterial adjacent the fin, forming a gate electrode comprised ofgraphene, wherein at least the layer of gate insulation material ispositioned between the gate electrode and the fin, and forming aninsulating material on the gate electrode. In some embodiments, the stepof forming the layer of gate insulation material is performed prior tothe step of forming the gate electrode, while, in other embodiments, thestep of forming the layer of gate insulation material is performed afterthe step of forming the gate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1A-1F depict one illustrative method disclosed herein of forming aFinFET device with a gate electrode comprised of graphene;

FIGS. 2A-2F depict another illustrative method disclosed herein offorming a FinFET device with a gate electrode comprised of graphene; and

FIGS. 3A-3L depict yet another illustrative method disclosed herein offorming a FinFET device with a gate electrode comprised of graphene.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

The present disclosure is directed to a FinFET device with a gateelectrode comprised of graphene and various methods of forming suchFinFET devices. As will be readily apparent to those skilled in the artupon a complete reading of the present application, the present methodis applicable to a variety of devices, including, but not limited to,logic devices, memory devices, etc. Moreover, the techniques disclosedherein may be employed to form N-type and/or P-type FinFET devices. Withreference to the attached figures, various illustrative embodiments ofthe methods and devices disclosed herein will now be described in moredetail.

FIGS. 1A-1F depict one illustrative method disclosed herein of forming aFinFET device 100 with a gate electrode comprised of one or moremonolayers of graphene. In a FinFET device, the height or thickness ofthe gate electrode is a very important characteristic because thegreater the height or thickness of the gate electrode, the greater themagnitude of parasitic gate-to-source and gate-to-drain capacitances. Ingeneral, the formation of a FinFET device involves the formation of oneor more fins in a semiconducting substrate. As will be understood bythose skilled in the art after a complete reading of the presentapplication, the fins for the FinFET devices disclosed herein may bemanufactured using any desired technique. For example, the fins may beformed prior to filling various trenches that will eventually becomeisolation structures for the FinFET device with an insulating material.The fins may also be formed using a so-called damascene-like technique.In the damascene-like technique, a plurality of trenches are formed inthe substrate that defines the fins and the isolation trenches, all ofthe trenches are filled with an insulating material, an etch mask isformed to cover the isolation regions while exposing the region wherethe fins will be formed, and an etch process is performed that isnon-selective relative to the substrate and the insulating material. Thenon-selective etch process is performed for a sufficient duration suchthat a portion of the thickness of the layer of insulating material inthe fin region is removed which thereby exposes the fins to the desiredheight. Thus, the present invention should not be considered as limitedto any particular technique for manufacturing the fins of a FinFETdevice.

FIG. 1A is a simplified view of an illustrative FinFET semiconductordevice 100 that is formed in and above an illustrative semiconductingsubstrate 10. The substrate 10 may have a variety of configurations,such as the depicted bulk configuration, or it may have otherconfigurations, such as, for example, a so-called silicon-on-insulator(SOI) configuration. The substrate (or at least the fins) 10 may be madeof silicon or they may be made of any other semiconductor material, suchas silicon, silicon/germanium, a III-V compound semiconductor material,a II-VI compound semiconductor material, or silicon/carbon orcombinations thereof, etc. FIG. 1A depicts the illustrative FinFETdevice 100 at the point of fabrication wherein a patterned mask layer16, such as a patterned hard mask layer, has been formed above thesubstrate 10 using known photolithography and etching techniques.Thereafter, an etching process, such as a dry or wet etching process, isthen performed on the substrate 10 through the patterned mask layer 16to form a plurality of trenches 14. This etching process results in thedefinition of a plurality of fins 20. In some applications, a furtheretching process may be performed to reduce the width or to “thin” thefins 20, although such a thinning process is not depicted in theattached drawings. For purposes of this disclosure and the claims, theuse of the terms “fin” or “fins” should be understood to refer to finsthat have not been thinned as well as fins that have been subjected tosuch a thinning etch process. The overall size, shape and configurationof the trenches 14 and fins 20 may vary depending on the particularapplication. The depth 14D and width 14W of the trenches 14 may varydepending upon the particular application. In one illustrativeembodiment, based on current day technology, the depth 14D of thetrenches 14 may range from approximately 30-150 nm and the width 14W ofthe trenches 14 may range from about 20-50 nm. In some embodiments, thefins 20 may have a final width 20W within the range of about 5-30 nm. Inthe illustrative example depicted in FIGS. 1A-1F, the trenches 14 andfins 20 are all of a uniform size and shape. However, such uniformity inthe size and shape of the trenches 14 and the fins 20 is not required topractice at least some aspects of the inventions disclosed herein. Inthe example depicted herein, the trenches 14 are formed by performing ananisotropic etching process that results in the trenches 14 having aschematically depicted, generally rectangular configuration. In anactual real-world device, the sidewalls of the trenches 14 may besomewhat inwardly tapered, although that configuration is not depictedin the drawings. In some cases, the trenches 14 may have a reentrantprofile near the bottom of the trenches 14. To the extent the trenches14 are formed by performing a wet etching process, the trenches 14 maytend to have a more rounded configuration or non-linear configuration ascompared to the generally rectangular configuration of the trenches 14that are formed by performing an anisotropic etching process. Thus, thesize and configuration of the trenches 14, and the manner in which theyare made, should not be considered a limitation of the presentinvention. For ease of disclosure, only the substantially rectangulartrenches 14 will be depicted in subsequent drawings.

Then, as shown in FIG. 1B, a layer of insulating material 22 is formedin the trenches 14 of the device 100. The layer of insulating material22 may be comprised of a variety of different materials, such as silicondioxide, silicon oxynitride, SiCN, etc., and it may be formed byperforming a variety of techniques, e.g., chemical vapor deposition(CVD), spin-coating, etc. In one illustrative embodiment, the layer ofinsulating material 22 may be a flowable oxide material that is formedby performing a CVD process. Such a flowable oxide material is adaptedfor use with fins 20 of different configurations, even fins 20 with areentrant profile. In the example depicted in FIG. 1B, the surface 22Sof the layer of insulating material 22 is the “as-deposited” surface ofthe layer 22. In this example, the surface 22S of the layer ofinsulating material 22 may be positioned slightly above the uppersurface 16S of the mask layer 16. Portions of the insulating material 22will eventually become the local isolation regions between the fins 20.

Next, as shown in FIG. 1C, one or more chemical mechanical polishing(CMP) processes may be performed to planarize the surface 22S using themask layer 16 as a polish stop layer. After such a CMP process, thesurface 22S of the layer of insulating material 22 is substantiallylevel with the surface 16S of the mask layer 16.

FIG. 1D depicts the device 100 after several process operations havebeen performed. First, an etching process was performed to reduce thethickness of the layer of insulating material 22. This process resultedin the layer of insulating material having a recessed surface 22R. Therecessing of the layer of insulating material 22 defines the approximatefinished height of the fins 20 for the completed device. In oneillustrative example, the final fin height of the fins 20 may range fromabout 5-50 nm. Additionally, another etching process was performed toremove the patterned hard mask layer 16. Thereafter, a layer of gateinsulating material 24 is conformably deposited on the fins 20 and abovethe layer of insulating material 22. In one illustrative embodiment, thelayer of gate insulating material 24 may be comprised of a material suchas, for example, silicon dioxide, silicon nitride, hafnium oxide, ahigh-k (k value greater than 10) insulating material, etc., it may beformed by performing a variety of known techniques, e.g., atomic layerdeposition (ALD), chemical vapor deposition (CVD), etc., and itsthickness may vary depending upon the particular application. In oneparticular example, the layer of gate insulation material 24 may be alayer of high-k insulating material having a thickness of about 2-3 nm.

Next, as shown in FIG. 1E, a graphene formation process 25 is performedto form graphene material 26 on the layer of gate insulation material24. In one illustrative example, the graphene formation process 25 is aspin-coating process wherein graphene colloids are coated on the exposedsurfaces, including the exposed surfaces of the layer of gate insulationmaterial 24, and thereafter allowed to dry so as to form the conductivegraphene material 26, which may be comprised of one or more monolayersof graphene. In one illustrative example, the graphene material 26 willfunction as the gate electrode for the FinFET device 100. In oneexample, the process 25 uses dilute chemically converted graphene andair-sprays them onto the device 100, wherein the process may beperformed at room temperature. In general, for relatively small-sizedsubstrates, the graphene colloids may be sprayed on the substrate,while, for larger substrates, the colloids may be applied by aspin-coating process.

After the graphene material 26 is formed, a masking layer, such as apatterned hard mask layer (not shown), may be formed above the channelregion of the device 100. Thereafter, portions of the graphene material26 and the layer of gate insulation material 24 that are not covered bythe masking layer may be removed. For example, a plasma-based ashingprocess may be performed to remove the exposed portions of the graphenematerial 26 and a dry etching process may thereafter be performed toremove the exposed portions of the layer of gate insulation material 24.Thereafter, sidewall spacers (not shown) may be formed adjacent the gatestructure for the device 100, i.e., adjacent the layer of gateinsulating material 24 and the graphene gate electrode 26, by depositinga layer of spacer material, e.g., silicon nitride, and thereafterperforming an anisotropic etching process.

FIG. 1F depicts the device 100 after a layer of insulating material 28and a plurality of conductive gate contacts 30 have been formed on thedevice 100. The layer of insulating material 28 may be comprised of avariety of different materials, e.g., silicon dioxide, a low-kinsulating material (k value less than about 3), etc., and it may beformed using traditional techniques, e.g., by performing a CVD or ALDprocess. The conductive gate contacts 30 may be comprised of a varietyof different materials, e.g., nickel, titanium, palladium, etc., andthey may be formed using traditional techniques used to form conductivecontacts, e.g., damascene techniques.

FIGS. 2A-2F depict another illustrative method disclosed herein offorming a FinFET device 100 with a gate electrode comprised of graphene.FIG. 2A depicts the FinFET device 100 at the point of fabrication thatcorresponds to that shown in FIG. 1D. That is, the layer of insulatingmaterial 22 has been recessed and the layer of gate insulation material24 has been formed as previously described.

In this illustrative process flow, as shown in FIG. 2B, a layer of metalor a metal alloy 32 is formed on the gate insulation layer 24. The layer32 may be made of any type of metal, copper, aluminum, nickel, tungsten,etc., and it may be formed by performing a variety of known techniques,e.g., electroplating, physical vapor deposition, etc. To the extent thatany barrier and/or seed layers are employed in forming the layer 32,those layers are not depicted in the drawings so as not to obscure thepresentation of the various inventions disclosed herein. As an example,in the case where the metal or metal alloy 32 is comprised of copper, abarrier layer (not shown) of, for example, tantalum may be formed priorto formation of the copper metal or metal alloy so as to reduce orprevent migration of copper.

Next, as shown in FIG. 2C, a graphene growth formation process 34 isperformed to form one or more monolayers of graphene material 26. Inthis illustrative embodiment, the graphene formation process 34 is aselective CVD-based growth process, whereby the graphene material 26forms on the outer surfaces of the layer of metal 32, even where theouter surface of the layer of metal 32 is resting on the layer of gateinsulating material 24. In one illustrative example, the graphene growthformation process 34 may be a CVD-based process that is performed for aduration of approximately 25 minutes at a temperature within the rangeof about 900-1000° C., at a pressure of about 500 mTorr using a flowrate of about 35 sscm of methane (CH₄) .

At this point, the work function of the graphene material 26 may beadjusted by depositing appropriate so-called SAMs (self-assembledmonolayers). In one illustrative embodiment, SAMs such as amine (NH₂) ormethyl (CH₃), etc., are used to adjust the work function of the graphenematerial 26. In general, a SAM such as amine effectively donateselectrons to the graphene material while a SAM effectively attracts orremoves electrons from the graphene material 26.

Then, as shown in FIG. 2D, a plasma-based ashing process may beperformed to remove the exposed portions of the graphene material 26selectively relative to the layer of metal 32. FIG. 2E depicts thedevice 100 after a dry or wet etching process has been performed toremove the exposed layer of metal 32 selectively relative to thegraphene material 26. This leaves the remaining portions of the graphenematerial 26 on the layer of gate insulation material 24. The workfunction of the graphene material 26 may then be adjusted by depositingone or more SAMs, as described above. Then, as before, a masking layer,such as a patterned hard mask layer (not shown), may be formed above thechannel region of the device 100. Thereafter, portions of the graphenematerial 26 and the layer of gate insulation material 24 that are notcovered by the masking layer may be removed. For example, a plasma-basedashing process may be performed to remove the exposed portions of thegraphene material 26 and a dry etching process may thereafter beperformed to remove the exposed portions of the layer of gate insulationmaterial 24. Thereafter, sidewall spacers (not shown) may be formedadjacent the gate structure for the device 100, i.e., adjacent the layerof gate insulating material 24 and the graphene gate electrode 26, bydepositing a layer of spacer material, e.g., silicon nitride, andthereafter performing an anisotropic etching process. FIG. 2F depictsthe device 100 after the layer of insulating material 28 and theplurality of conductive gate contacts 30 have been formed on the device100, as previously described.

FIGS. 3A-3L depict yet another illustrative method disclosed herein offorming a FinFET device 100 with a gate electrode comprised of graphene.FIG. 3A depicts the FinFET device 100 at the point of fabrication afterseveral process operations have been performed. First, the fins 20 andthe layer of insulating material 22 were formed and the layer ofinsulating material 22 was recessed as described previously, inconnection with the process flow described previously up to the pointdepicted in FIG. 1D. Next, a layer of insulating material 38 isconformably deposited on the device 100. In one illustrative embodiment,the layer of insulating material 38 may be comprised of a material suchas, for example, silicon dioxide, etc., it may be formed by performing avariety of known techniques, e.g., ALD, CVD, etc., and its thickness mayvary depending upon the particular application. In one particularexample, the layer of insulation material 38 may be a layer of silicondioxide having a thickness of about 1-2 nm. Thereafter, another layer ofinsulating material 40 is conformably deposited on the layer ofinsulating material 38. In general, the layer of insulating material 40should be made of a material that is selectively etchable relative tothe layer of insulating material 38. In one illustrative embodiment, thelayer of insulating material 40 may be a layer of silicon nitride havinga thickness of about 1-5 nm, and it may be formed by performing, forexample, an ALD process.

Next, as shown in FIG. 3B, the previously described layer of metal or ametal alloy 32 is formed on the device 100. As noted previously, to theextent that any barrier and/or seed layers are employed in forming thelayer 32, those layers are not depicted in the drawings so as not toobscure the presentation of the various inventions disclosed herein. Themetal layer 32 may be formed by directly depositing the metal layer 32so as to overfill the trenches and thereafter performing a CMP processto remove excess portions of the layer of metal 32.

Then, as shown in FIG. 3C, an etching process, such as a wet etchingprocess, is performed to remove exposed portions of the layer ofinsulating material 40 relative to the layer of metal 32 and the layerof insulating material 38. This process results in the definition of aplurality of cavities 44, i.e., regions that were formerly occupied bythe layer of insulating material 40.

Next, as shown in FIG. 3D, the previously described graphene formationprocess 34 is performed to form one or more monolayers of graphenematerial 26. As noted before, the graphene formation process 34 is aselective CVD-based growth process, whereby the graphene material 26forms on the outer surfaces of the layer of metal 32, even where theouter surface of the layer of metal 32 is resting on the layer ofinsulating material 40. The work function of the graphene material 26may then be adjusted by depositing one or more SAMs, as described above.

Then, as shown in FIG. 3E, a conformable deposition process, e.g., anALD process, is performed to form the previously described layer of gateinsulating material 24 in the cavities 44 (between the layer ofinsulating material 40 and the graphene material 26) and above the fins20. As part of this deposition process, portions of the layer of gateinsulating material 24 may form above portions of the metal layer 32,and they may be removed by performing a CMP process using the metallayer 32 as a polish stop layer.

Thereafter, as shown in FIG. 3F, a patterned mask layer 48, such as apatterned hard mask layer, is formed above the device 100 so as toexpose regions above the fins 20. The patterned mask layer 48 may becomprised of a variety of materials, e.g., silicon dioxide, and it maybe formed using traditional deposition, photolithography and etchingtools and techniques.

Next, as shown in FIG. 3G, another layer of metal 32A that is similar tothe previously described layer of metal or a metal alloy 32 is formed onthe device 100. As noted previously, to the extent that any barrierand/or seed layers are employed in forming the layer 32A, those layersare not depicted in the drawings so as not to obscure the presentationof the various inventions disclosed herein. The metal layer 32A may beformed by directly depositing the metal layer 32A so as to overfill thetrenches defined by the patterned mask layer 48 and thereafterperforming a CMP process to remove excess portions of the layer of metal32A using the patterned mask layer 48 as a polish stop layer.

Next, as shown in FIG. 3H, the previously described graphene formationprocess 34 is performed yet again to form one or more monolayers ofgraphene material 26A. As noted before, the graphene formation process34 is a selective CVD-based growth process, whereby the graphenematerial 26 forms on the outer surfaces of the layer of metal 32A, evenwhere the outer surface of the layer of metal 32A is resting on thelayer of gate insulating material 24. The graphene material 26Aconductively contacts the graphene material 26.

Then, as shown in FIG. 31, an etching process, such as a wet etchingprocess, is performed to remove the patterned mask layer 48 selectivelyrelative to all adjacent materials.

Next, as shown in FIG. 3J, a plasma-based ashing process may beperformed to remove the exposed portions of the graphene materials 26Aand 26 selectively relative to the layers of metal 32A, 32. The processexposes the layers of metal 32A, 32 for further processing. For example,at this point, the work function of the residual portions of the layersof metal (or metal alloy) 32A, 32 may be adjusted by depositing one ormore of the SAMs identified above.

FIG. 3K depicts the device 100 after a dry or wet etching process hasbeen performed to remove the exposed portions of the layers of metal32A, 32 selectively relative to the graphene materials 26A, 26. Thisleaves the remaining portions of the graphene materials 26A, 26positioned on the layer of gate insulation material 24. Then, as before,a masking layer, such as a patterned hard mask layer (not shown), may beformed above the channel region of the device 100. Thereafter, portionsof the graphene materials 26A, 26 and the layer of gate insulationmaterial 24 that are not covered by the masking layer may be removed.For example, a plasma-based ashing process may be performed to removethe exposed portions of the graphene materials 26A, 26 and a dry etchingprocess may thereafter be performed to remove the exposed portions ofthe layer of gate insulation material 24. Thereafter, sidewall spacers(not shown) may be formed adjacent the gate structure for the device100, i.e., adjacent the layer of gate insulating material 24 and thegraphene gate electrode materials 26A, 26, by depositing a layer ofspacer material, e.g., silicon nitride, and thereafter performing ananisotropic etching process. FIG. 3L depicts the device 100 after thelayer of insulating material 28 and the plurality of conductive gatecontacts 30 have been formed on the device 100, as previously described.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

1. A FinFET device, comprising: at least one fin comprised of asemiconducting material; a layer of gate insulation material positionedadjacent an outer surface of said fin; a gate electrode comprised ofgraphene positioned on said layer of gate insulation material around atleast a portion of said fin; and an insulating material formed on saidgate electrode.
 2. The device of claim 1, wherein said semiconductingmaterial is comprised of one of silicon, silicon/germanium, a III-Vcompound semiconductor material, a II-VI compound semiconductormaterial, or silicon/carbon or combinations thereof
 3. The device ofclaim 1, wherein said gate insulation material is comprised of silicondioxide or a high-k insulating material.
 4. The device of claim 1,wherein said layer of gate insulation material is positioned on saidouter surface of said fin.
 5. The device of claim 4, wherein said layerof gate insulation material is positioned on an upper surface and twoside surfaces of said fin.
 6. The device of claim 1, wherein said gateelectrode is positioned above an upper surface and two side surfaces ofsaid fin.
 7. The device of claim 1, further comprising at least oneconductive contact positioned in said layer of insulating material thatis conductively coupled to said gate electrode.
 8. A FinFET device,comprising: at least one fin comprised of a semiconducting material; alayer of gate insulation material that is positioned above an uppersurface and two side surfaces of said fin, said layer of gate insulationmaterial comprising a high-k insulating material; a gate electrodecomprised of graphene positioned on said layer of gate insulationmaterial, said gate electrode being positioned above said upper surfaceand said two side surfaces of said fin; and an insulating materialformed on said gate electrode.
 9. The device of claim 8, wherein saidlayer of gate insulation material is positioned on said upper surfaceand on said two side surfaces of said fin. 10.-23. (canceled)
 24. AFinFET device, comprising: at least one fin comprised of silicon; alayer of high-k gate insulation material positioned on an upper surfaceand two side surfaces of said fin; a graphene gate electrode positionedon said layer of gate insulation material around at least a portion ofsaid fin; and an insulating material formed on said gate electrode.